Lines Matching defs:handle
66 static int32_t chal_sd_set_power(struct sd_dev *handle,
69 static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary);
71 static int32_t chal_sd_setup_handler(struct sd_dev *handle,
78 static int32_t chal_sd_set_power(struct sd_dev *handle,
84 if (handle == NULL)
87 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr +
101 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr +
119 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
123 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0);
124 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0);
132 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr +
159 static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary)
161 if (handle == NULL)
164 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr +
169 static int32_t chal_sd_setup_handler(struct sd_dev *handle, uint32_t sdBase,
172 if (handle == NULL)
175 handle->ctrl.sdRegBaseAddr = sdBase;
176 handle->ctrl.hostRegBaseAddr = hostBase;
177 handle->ctrl.present = 0;
178 handle->ctrl.rca = 0;
179 handle->ctrl.blkGapEnable = 0;
180 handle->ctrl.cmdStatus = 0;
193 struct sd_dev *handle;
200 handle = (struct sd_dev *)sd_handle;
252 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
256 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
260 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET,
262 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET,
267 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET,
269 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET,
273 cap_val_l = mmio_read_32(handle->ctrl.sdRegBaseAddr +
275 handle->cfg.voltage = 0;
279 handle->cfg.voltage |= SD_VDD_WINDOW_3_3_TO_3_4;
282 handle->cfg.voltage |= SD_VDD_WINDOW_3_0_TO_3_1;
285 handle->cfg.voltage |= SD_VDD_WINDOW_1_8_TO_1_9;
289 rval = chal_sd_set_power(handle, voltage, SD4_EMMC_TOP_CTRL_SDPWR_MASK);
291 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
293 handle->ctrl.version = ((ctl_val >> 16) & 0xFF);
300 struct sd_dev *handle;
305 handle = (struct sd_dev *) sd_handle;
309 mmio_setbits_32(handle->ctrl.sdRegBaseAddr +
314 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr +
342 struct sd_dev *handle;
347 handle = (struct sd_dev *) sd_handle;
349 if (caps & mmio_read_32(handle->ctrl.sdRegBaseAddr +
360 struct sd_dev *handle;
366 handle = (struct sd_dev *) sd_handle;
368 handle->cfg.mode = SD_PIO_MODE; /* set to PIO mode first for init */
369 handle->cfg.dma = SD_DMA_OFF;
371 chal_sd_setup_handler(handle, sd_base, host_base);
380 handle->ctrl.eventList = 0;
381 handle->cfg.mode = mode;
391 struct sd_dev *handle;
396 handle = (struct sd_dev *) sd_handle;
398 return (mmio_read_32(handle->ctrl.sdRegBaseAddr +
407 struct sd_dev *handle;
412 handle = (struct sd_dev *) sd_handle;
414 return mmio_read_32(handle->ctrl.sdRegBaseAddr +
424 struct sd_dev *handle;
429 handle = (struct sd_dev *)sd_handle;
431 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
452 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
464 struct sd_dev *handle;
470 handle = (struct sd_dev *)sd_handle;
481 handle->cfg.dma = mode;
482 val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
485 val |= handle->cfg.dma - 1;
486 mmio_write_32(handle->ctrl.sdRegBaseAddr +
491 handle->cfg.dma = 0;
502 struct sd_dev *handle;
507 handle = (struct sd_dev *) sd_handle;
509 if (handle->cfg.dma == SD_DMA_OFF)
512 return (uintptr_t)mmio_read_32(handle->ctrl.sdRegBaseAddr +
520 struct sd_dev *handle;
525 handle = (struct sd_dev *) sd_handle;
537 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_BLOCK_OFFSET,
538 handle->ctrl.blkReg);
541 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET,
543 handle->ctrl.argReg = argument;
551 cmd_mode_reg |= ((handle->cfg.dma) ? 1 : 0);
553 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET,
556 handle->ctrl.cmdIndex = cmd_idx;
563 struct sd_dev *handle;
568 handle = (struct sd_dev *) sd_handle;
570 if (handle->cfg.dma == SD_DMA_OFF)
573 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET,
616 struct sd_dev *handle;
627 handle = (struct sd_dev *) sd_handle;
630 value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
636 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
651 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
656 value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
672 value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
678 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
693 struct sd_dev *handle;
698 handle = (struct sd_dev *) sd_handle;
700 if (length <= handle->cfg.blockSize) {
701 handle->ctrl.blkReg = length | handle->cfg.dmaBoundary;
703 blocks = length / handle->cfg.blockSize;
704 handle->ctrl.blkReg = (blocks << 16) | handle->cfg.blockSize |
705 handle->cfg.dmaBoundary;
708 if (handle->cfg.dma != SD_DMA_OFF) {
710 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET,
728 struct sd_dev *handle;
733 handle = (struct sd_dev *) sd_handle;
735 blockSize = handle->cfg.blockSize;
750 mmio_write_32(handle->ctrl.sdRegBaseAddr +
766 mmio_write_32(handle->ctrl.sdRegBaseAddr +
783 struct sd_dev *handle;
788 handle = (struct sd_dev *)sd_handle;
792 blockSize = handle->cfg.blockSize;
805 mmio_read_32(handle->ctrl.sdRegBaseAddr +
811 value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
834 struct sd_dev *handle;
839 handle = (struct sd_dev *) sd_handle;
846 control = mmio_read_32(handle->ctrl.sdRegBaseAddr +
849 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
854 control = mmio_read_32(handle->ctrl.sdRegBaseAddr +
867 struct sd_dev *handle;
872 handle = (struct sd_dev *) sd_handle;
873 resp[0] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
875 resp[1] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
877 resp[2] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
879 resp[3] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
891 struct sd_dev *handle;
896 handle = (struct sd_dev *)sd_handle;
900 mmio_write_32(handle->ctrl.sdRegBaseAddr +
903 } while (mmio_read_32(handle->ctrl.sdRegBaseAddr +
914 struct sd_dev *handle;
919 handle = (struct sd_dev *) sd_handle;
921 return (mmio_read_32(handle->ctrl.sdRegBaseAddr +
930 struct sd_dev *handle;
935 handle = (struct sd_dev *) sd_handle;
939 mmio_write_32(handle->ctrl.sdRegBaseAddr +
943 mmio_read_32(handle->ctrl.sdRegBaseAddr +
955 struct sd_dev *handle;
960 handle = (struct sd_dev *) sd_handle;
962 handle->cfg.speedMode = speed;
963 handle->cfg.retryLimit = retry;
964 handle->cfg.dmaBoundary = boundary;
965 handle->cfg.blockSize = blkSize;
969 chal_sd_set_dma_boundary(handle, boundary);
983 struct sd_dev *handle;
988 handle = (struct sd_dev *)sd_handle;
991 while (mmio_read_32(handle->ctrl.sdRegBaseAddr +
993 mmio_read_32(handle->ctrl.sdRegBaseAddr +
1004 struct sd_dev *handle;
1009 handle = (struct sd_dev *)sd_handle;
1012 mmio_setbits_32(handle->ctrl.sdRegBaseAddr +
1015 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr +