Lines Matching defs:base
19 #define GIC_FMU_WRITE_32(base, reg, val) \
25 mmio_write_32(base + GICFMU_KEY, 0xBE); \
27 mmio_write_32((base) + (reg), (val)); \
31 #define GIC_FMU_WRITE_64(base, reg, n, val) \
37 mmio_write_32(base + GICFMU_KEY, 0xBE); \
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
47 static void wait_until_fmu_is_idle(uintptr_t base)
54 status = (gic_fmu_read_status(base) & BIT(0));
66 #define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \
69 wait_until_fmu_is_idle(base); \
71 GIC_FMU_WRITE_32(base, reg, val); \
73 wait_until_fmu_is_idle(base); \
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \
79 wait_until_fmu_is_idle(base); \
81 GIC_FMU_WRITE_64(base, reg, n, val); \
83 wait_until_fmu_is_idle(base); \
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n)
100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U);
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32);
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n)
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U);
118 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32);
126 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n)
132 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U);
134 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32);
141 uint64_t gic_fmu_read_errgsr(uintptr_t base)
147 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO);
149 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRGSR_HI) << 32);
156 uint32_t gic_fmu_read_pingctlr(uintptr_t base)
158 return mmio_read_32(base + GICFMU_PINGCTLR);
164 uint32_t gic_fmu_read_pingnow(uintptr_t base)
166 return mmio_read_32(base + GICFMU_PINGNOW);
172 uint64_t gic_fmu_read_pingmask(uintptr_t base)
178 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_PINGMASK_LO);
180 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_PINGMASK_HI) << 32);
187 uint32_t gic_fmu_read_status(uintptr_t base)
189 return mmio_read_32(base + GICFMU_STATUS);
195 uint32_t gic_fmu_read_erridr(uintptr_t base)
197 return mmio_read_32(base + GICFMU_ERRIDR);
203 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val)
205 GIC_FMU_WRITE_64(base, GICFMU_ERRCTLR, n, val);
212 void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val)
215 GIC_FMU_WRITE_ON_IDLE_64(base, GICFMU_ERRSTATUS, n, val);
221 void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val)
223 GIC_FMU_WRITE_32(base, GICFMU_PINGCTLR, val);
229 void gic_fmu_write_pingnow(uintptr_t base, uint32_t val)
232 GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_PINGNOW, val);
238 void gic_fmu_write_smen(uintptr_t base, uint32_t val)
241 GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMEN, val);
248 void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val)
251 GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMINJERR, val);
257 void gic_fmu_write_pingmask(uintptr_t base, uint64_t val)
259 GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
265 void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid)
302 gic_fmu_write_smen(base, smen);