Lines Matching defs:core_addr

34 #define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
35 	(core_addr + reg_offset)
120 static bool ethosn_get_device_and_core(uintptr_t core_addr,
133 			if (core->addr == core_addr) {
146 static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
148 	uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
185 static void ethosn_configure_vector_table(uintptr_t core_addr)
187 	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG),
193 static void ethosn_configure_events(uintptr_t core_addr)
195 	mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL1_REG), SEC_SYSCTRL1_VAL);
199 					  uintptr_t core_addr,
217 	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_AUXCTLR_REG), val);
252 						 uintptr_t core_addr)
272 		mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, reg_addr),
277 static void ethosn_configure_stream_attr_ctlr(uintptr_t core_addr)
284 		mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, reg_addr),
289 static void ethosn_delegate_to_ns(uintptr_t core_addr)
291 	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
294 	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
297 	mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
301 static int ethosn_is_sec(uintptr_t core_addr)
303 	if ((mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG))
311 static int ethosn_core_is_sleeping(uintptr_t core_addr)
314 		ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
320 static bool ethosn_core_reset(uintptr_t core_addr, bool hard_reset)
324 		ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
344 static int ethosn_core_boot_fw(uintptr_t core_addr)
347 	const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
442 					 u_register_t core_addr,
453 	if (!ethosn_get_device_and_core(core_addr, &device, &core))  {