Lines Matching defs:only

71 -  Regions accessible from only the secure state. For example, trusted SRAM and
75    which is accessible only from the secure state.
168 This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
243       Design Guide are supported for AArch64 only. These SMCs are currently
431 as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
506 is the only mechanism to access the runtime services implemented by BL31 (PSCI
572 Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
587 This function must only be called by the primary CPU.
707 This function must only be called by the primary CPU.
895 function is only invoked on the primary CPU during cold boot. If the service
1157    which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower
1180    that continue with original exception. It is the only scenario where EL3 is capable
1386 Please note that only 2. is mandated by the TRM.
1445 array and returns it. Note that only the part number and implementer fields
1451 body may only clobber x0 to x14 with x14 being the cpu_rev parameter.
1517    It may only clobber x0 to x4. The rest should be treated as callee-saved.
1524    It may only clobber x0 to x8. The rest should be treated as callee-saved.
1582 Reporting the status of errata workaround is for informational purpose only; it
1670 -  The MMU setup code needs to know the extents of the coherent and read-only
1673    read-only memory region is divided between code and data.
1783    remain valid only until execution reaches the EL3 Runtime Software entry
1793    -  Trusted DRAM (FVP only)
1824 (These diagrams only cover the AArch64 case)
2116 only supports packing bootloader images. Additional image definitions can be
2133 The Arm development platforms' policy is to only allow loading of a known set of
2214 ``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2215 them from coherent memory involves only doing a clean and invalidate of the
2243 fields can be read by all CPUs but only written to by the owning CPU.
2263 algorithm mentioned earlier. The bakery_lock structure only allocates the memory
2363 Isolating code and read-only data on separate memory pages
2386        |  Read-only data   |
2396 read-write permissions, whereas the code and read-only data below are configured
2397 as read-only.
2399 However, the read-only data are not aligned on a page boundary. They are
2401 of the read-only data one might share a memory page. This forces both to be
2403 means that the read-only data stored on the same memory page as the code are
2408 read-only data on separate memory pages. This in turn allows independent control
2409 of the access permissions for the code and read-only data. In this case,
2411 appropriately map the code region as executable and the read-only data as
2415 between the code and read-only data to ensure the segregation of the two. To
2427        |  Read-only data   |
2438 With this more condensed memory layout, the separation of read-only data will
2491 PE only; it won't cause handlers to execute on a different PE.
2607 The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2729    Notice this instruction is only available in AArch64 execution state, so
2730    the option is only available to AArch64 builds.
2771    (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2772    implemented at all ELs, it is unconditionally enabled for only the normal
2841 defined by the build system. This enables TF-A to compile certain code only